I'm an Electrical Engineer passionate about FPGAs, hardware design, embedded systems, fault-tolerant systems, domain-specific architectures, digital signal/image processing and machine learning.
I hold a BSEE from the Federal University of Rio Grande do Norte (UFRN) and I'm currently pursuing a MSEE at the State University of Campinas (UNICAMP).
My BS final project was the implementation of a 5-stage pipeline RV32I RISC-V CPU Core written in VHDL.
I did my internship at the National Institute for Space Research, working at the ARGOS-II Environmental Data Collector Cubesat payload.
I'm currently working as a software engineer at Eldorado Research Institute/Motorola Mobility.
Machine Learning Super-Resolution Part 2 - Can We Beat Waifu2x?
Gamma Correction - Why You Should Care
Domain-Specific Accelerators - A Short Preface
Machine Learning Super-Resolution - An Introduction to AI Upsampling
Building a Pipelined CPU Core - An Introduction to Computer Architecture and Digital Design
Open Hardware and RISC-V - A Brief Introduction
Interning at the Brazilian National Institute for Space Research
Keyframe Encoding Comparison - Numerically Evaluating Different Popular Video Encoders on Anime Content
Evaluating mpv's Upscaling Algorithms - A Study of Performance and Quality
Digital Image Processing - University Assignments
Assigned to work alongside Motorola on ISP pipelines, imaging algorithms and auto-focus for camera systems in Android devices.
Assigned primarily at developing and maintaining the testbench of a SBCDA (Brazilian Environmental Data Collection System) Cubesat compatible payload, including a hardware in the loop test-routine
and the required code to emulate an on-board-computer utilising an x86 Workstation running Matlab as a master, an Arduino Due as an I²C bridge and a Rohde&Schwarz SMBV100A Vector Signal Generator.
Secondary tasks varied from firmware development to brainstorming possible engineering solutions or improvements to the Environmental Data Collector as a whole, which included changes to the dedicated decoding hardware in the Microsemi Smartfusion 2 FPGA, or to the communication protocols handled by the ARM Cortex-M3 based microcontroller subsystem running FreeRTOS.
Updating internal and external use documentation was also part of the daily routine, on top of sometimes interacting with external teams integrating our system alongside their on-board-computers.
I'm currently studying super-resolution CNNs and ML optimisation techniques for fast inference.
My grad level classes included internet of things, digital signal processing and machine learning.
Developed Maestro, a 5-stage pipeline in-order RV32I RISC-V core written entirely in VHDL for academic purposes. Intel Quartus Prime and ModelSim were utilised for synthesis and verification, and a Cyclone V FPGA was used for testing purposes. The core is part of my bachelor’s degree and can be found at https://riscv.org/risc-v-cores.
Conducted a performance and picture quality evaluation of different upscaling algorithms supported by the popular video player mpv, which includes a wide variety of choices, from polynomial interpolation to convolutional neural networks based shaders. The study was conducted for a Digital Image Processing subject and can be found at https://artoriuz.github.io/mpv_upscaling.html.
Undergrad classes included digital and analogue electronics, power systems, control systems, communication systems, embedded systems and artificial intelligence.
SP-VDSR is a shallow convolutional neural network based on both VDSR and ESPCN. The rationale was making VDSR faster employing ESPCN's depth-to-space sub-pixel convolution to upsample the residuals. The trained network is relatively shallow with only 5 convolutional layers of 8 kernels each.View Project
Maestro is a 5 stage pipeline implementation of the RV32I ISA strongly inspired by David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.
The project is entirely academic, it's written in VHDL in a beginner-friendly way so computer architecture students can also learn about hardware design.
The core is very good at demonstrating how to build simple workarounds for problems encountered within pipelined in-order CPU cores such as hazards and stalls.
The environmental data collector is a Cubsat-compatible payload capable of decoding up to 12 ARGOS-2 PTT signals.
During my internship I was in charge of developing a way of simulating the system to catch bugs and evaluate its performance. The testbench was composed of a hardware in the loop test-routine and the required code to emulate an on-board-computer utilising an x86 Workstation running Matlab as a master, an Arduino Due as an I²C bridge and a Rohde&Schwarz SMBV100A Vector Signal Generator.
Conducted a performance and picture quality evaluation of different upscaling algorithms supported by the popular video player mpv, which includes a wide variety of choices, from polynomial interpolation to convolutional neural-network based shaders and measurements such as SSIM and PSNR.View Project
Motus Camera is a movement detection surveillance program written in C++ using OpenCV.
Upon movement detection, the recording is then written to disk encoded into an AVC clip until the scene becomes still.
Magnetic lock prototype controlled by a PIC16 with a numpad made of push buttons and code wittren in ASM.View Project
Memory game implemented using Qsys, NIOS II soft core and a Cyclone II FPGA.View Project