I'm an Electrical Engineer passionate about embedded signal processing and machine learning.
I hold a MSc in Computer Engineering from the State University of Campinas (UNICAMP) and a BSc in Electrical Engineering from the Federal University of Rio Grande do Norte (UFRN).
My MSc dissertation was about accelerating SISR CNNs for integrated graphics.
My BS final project was the implementation of a 5-stage pipeline RV32I RISC-V CPU Core written in VHDL.
I did my internship at the National Institute for Space Research, working at the ARGOS-II Environmental Data Collector Cubesat payload.
My previous job was as a contractor at Motorola working on image processing for smartphone cameras.
I'm currently working as a contractor software engineer at Wind River via Encora.
mpv Resampling - A sequel in the making
ImageMagick Resampling - When doing it with mpv isn't enough...
Machine Learning Super-Resolution Part 2 - Can We Beat Waifu2x?
Gamma Correction - Why You Should Care
Domain-Specific Accelerators - A Short Preface
Machine Learning Super-Resolution - An Introduction to AI Upsampling
Building a Pipelined CPU Core - An Introduction to Computer Architecture and Digital Design
Open Hardware and RISC-V - A Brief Introduction
Interning at the Brazilian National Institute for Space Research
Keyframe Encoding Comparison - Numerically Evaluating Different Popular Video Encoders on Anime Content
Digital Image Processing - University Assignments
Assigned to work alongside Wind River on their distributed edge cloud infrastructure.
Assigned to work alongside Motorola on ISP pipelines, imaging algorithms and auto-focus for camera systems in Android devices.
Assigned primarily at developing and maintaining the testbench of a SBCDA (Brazilian Environmental Data Collection System) Cubesat compatible payload, including a hardware in the loop test-routine
and the required code to emulate an on-board-computer utilising an x86 Workstation running Matlab as a master, an Arduino Due as an I²C bridge and a Rohde&Schwarz SMBV100A Vector Signal Generator.
Secondary tasks varied from firmware development to brainstorming possible engineering solutions or improvements to the Environmental Data Collector as a whole,
which included changes to the dedicated decoding hardware in the Microsemi Smartfusion 2 FPGA, or to the communication protocols handled by the ARM Cortex-M3 based microcontroller subsystem running FreeRTOS.
Updating internal and external use documentation was also part of the daily routine, on top of sometimes interacting with external teams integrating our system alongside their on-board-computers.
My work is about accelerating Convolutional Neural Networks for real-time super-resolution on integrated GPUs.
My grad level classes included internet of things, digital signal processing and machine learning.
Developed Maestro, a 5-stage pipeline in-order RV32I RISC-V core written entirely in VHDL for academic purposes. Intel Quartus Prime and ModelSim were utilised for synthesis and verification, and a Cyclone V FPGA was used for testing purposes. The core is part of my bachelor’s degree and can be found at https://riscv.org/risc-v-cores.
Conducted a performance and picture quality evaluation of different upscaling algorithms supported by the popular video player mpv, which includes a wide variety of choices, from polynomial interpolation to convolutional neural networks based shaders. The study was conducted for a Digital Image Processing subject and can be found at https://artoriuz.github.io/mpv_upscaling.html.
Undergrad classes included digital and analogue electronics, power systems, control systems, communication systems, embedded systems and artificial intelligence.
Single-Image Super-Resolution Convolutional Neural Networks as GLSL shaders for mpv. The model is relatively simple with a feed-forward architecture, a single long-skip connection and a pixel shuffle layer to upscale the feature maps. Different degradation models and dataset preparation steps were used to tackle different problems, and the model is offered in various flavours.
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CfL is a GLSL shader that implements chroma upscaling based on the closed least squares solution for linear regression, inspired by the adoption of the same technique in modern video codecs. Since a simple linear regression obviously doesn't take into account pixel distance, the prediction is mixed with the output of a normal resampling filter based on how high the correlation between luma and chroma is.
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Joint Bilateral is a simple implementation of joint bilateral chroma upsampling in GLSL. It uses the luma plane as a guide to achieve sharper edges without introducing any ringing.
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Pixel Clipper is a GLSL shader for anti-ringing. It limits pixel magnitude after resampling to avoid overshooting and haloing.
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OSEE consists of a series of online courses and textbook recommendations that together cover most of the basic Electrical Engineering knowledge, similarly to a bachelor's degree.
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Maestro is a 5 stage pipeline implementation of the RV32I ISA strongly inspired by David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.
The project is entirely academic, it's written in VHDL in a beginner-friendly way so computer architecture students can also learn about hardware design.
The core is very good at demonstrating how to build simple workarounds for problems encountered within pipelined in-order CPU cores such as hazards and stalls.
The environmental data collector is a Cubsat-compatible payload capable of decoding up to 12 ARGOS-2 PTT signals.
During my internship I was in charge of developing a way of simulating the system to catch bugs and evaluate its performance. The testbench was composed of a hardware in the loop test-routine
and the required code to emulate an on-board-computer utilising an x86 Workstation running Matlab as a master, an Arduino Due as an I²C bridge and a Rohde&Schwarz SMBV100A Vector Signal Generator.
Conducted a performance and picture quality evaluation of different upscaling algorithms supported by the popular video player mpv, which includes a wide variety of choices, from polynomial interpolation to convolutional neural-network based shaders and measurements such as SSIM and PSNR.
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Motus Camera is a movement detection surveillance program written in C++ using OpenCV.
Upon movement detection, the recording is then written to disk encoded into an AVC clip until the scene becomes still.
Magnetic lock prototype controlled by a PIC16 with a numpad made of push buttons and code wittren in ASM.
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Memory game implemented using Qsys, NIOS II soft core and a Cyclone II FPGA.
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